SN74ABT843DBR.B中文资料德州仪器数据手册PDF规格书

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, Ceramic Chip

Carriers (FK), Ceramic Flat (W) Package,

and Plastic (NT) and Ceramic (JT) DIPs

description

The ’ABT843 9-bit latches are designed

specifically for driving highly capacitive or

relatively low-impedance loads. They are

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The nine transparent D-type latches provide true

data at the outputs.

A buffered output-enable (OE) input can be used

to place the nine outputs in either a normal logic

state (high or low logic levels) or a

high-impedance state. The outputs are also in the

high-impedance state during power-up and

power-down conditions. The outputs remain in the

high-impedance state while the device is powered

down. In the high-impedance state, the outputs

neither load nor drive the bus lines significantly.

The high-impedance state and increased drive

provide the capability to drive bus lines without

need for interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT843 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT843 is characterized for operation from –40°C to 85°C.