10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.94 Kbytes 页数：19 Pages

TI

德州仪器

10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

文件：896.49 Kbytes 页数：17 Pages

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10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

文件：399.74 Kbytes 页数：16 Pages

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具有 TTL 兼容型 CMOS 输入和三态输出的 10 通道、4.5V 至 5.5V 缓冲器

These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\\ or OE2\\) input is high, all ten outputs are in the high-impedance s • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation\n• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 \n• High-Impedance State During Power Up and Power Down\n• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shri;

TI

德州仪器

丝印：AB827；Package：SSOP(DB)；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.94 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：SSOP(DB)；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.94 Kbytes 页数：19 Pages

TI

德州仪器

10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.94 Kbytes 页数：19 Pages

TI

德州仪器