丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI

德州仪器