SN74ABT162823A中文资料具有三态输出的 18 位总线接口触发器数据手册TI规格书

描述 Description

These 18-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The ’ABT162823A devices can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN)\\ input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR)\\ input low causes the Q outputs to go low independently of the clock.
A buffered output-enable (OE)\\ input places the nine outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE\\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Members of the Texas Instruments Widebus™ Family
• Output Ports Have Equivalent 25- Series Resistors So No External Resistors Are Required
• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Ioff and Power-Up 3-State Support Hot Insertion
• Distributed VCC and GND Pins Minimize High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
Widebus is a trademark of Texas Instruments.