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SN65LVDS96数据手册集成电路(IC)的驱动器接收器收发器规格书PDF

厂商型号 |
SN65LVDS96 |
参数属性 | SN65LVDS96 封装/外壳为8-SOIC(0.154",3.90mm 宽);包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC)的驱动器接收器收发器;产品描述:IC RECEIVER 0/2 8SOIC |
功能描述 | Serdes(串行器/解串器)接收器 |
封装外壳 | 8-SOIC(0.154",3.90mm 宽) |
制造商 | TI Texas Instruments |
中文名称 | 德州仪器 美国德州仪器公司 |
数据手册 | |
更新时间 | 2025-8-8 22:58:00 |
人工找货 | SN65LVDS96价格和库存,欢迎联系客服免费人工找货 |
SN65LVDS96规格书详情
描述 Description
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.
The SN65LVDS96 is characterized for operation over ambient air temperatures of -40°C to 85°C.
特性 Features
• 3:21 Data Channel Compression at up to1.428 Gigabits/s Throughput
• Suited for Point-to-Point Subsystem Communication With Very Low EMI
• 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply and 250 mW (Typ)
• 5-V Tolerant SHTDN Input
• Rising Clock Edge Triggered Outputs
• Bus Pins Tolerate 4-kV HBM ESD
• Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
• Consumes A =-40°C to 85°C
• Replacement for the DS90CR216
技术参数
- 制造商编号
:SN65LVDS96
- 生产厂家
:TI
- Protocols
:Channel-Link I
- Parallel bus width(bits)
:21
- Signaling rate(Mbps)
:1428
- Input signal
:LVDS
- Output signal
:LVTTL
- Package Group
:TSSOP | 48
- Operating temperature range(C)
:-40 to 85
- Rating
:Catalog
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI |
2016+ |
TSSOP48 |
7393 |
只做原装,假一罚十,公司可开17%增值税发票! |
询价 | ||
TI |
06+ |
SOP8 |
3215 |
全新原装进口自己库存优势 |
询价 | ||
TI |
20+ |
MSOP |
65790 |
原装优势主营型号-可开原型号增税票 |
询价 | ||
TI |
24+ |
MSOP8 |
20000 |
全新原厂原装,进口正品现货,正规渠道可含税!! |
询价 | ||
TI |
23+ |
NA |
19854 |
专业电子元器件供应链正迈科技特价代理特价,原装元器件供应,支持开发样品 |
询价 | ||
TI/德州仪器 |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
询价 | |||
TI |
24+ |
SOP8 |
2568 |
原装优势!绝对公司现货 |
询价 | ||
TI |
2018+ |
26976 |
代理原装现货/特价热卖! |
询价 | |||
TI/德州仪器 |
1950+ |
TSSOP48 |
4856 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
TI |
24+ |
SOIC |
6000 |
进口原装正品假一赔十,货期7-10天 |
询价 |