具有清零端和三态输出的双路 J-K 触发器

The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these • Package Options Include Plastic “Small Outline\" Packages, Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

恩XP

恩智浦

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per f

恩XP

恩智浦