丝印：SN54LS73AJ；Package：CDIP；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

文件：810.42 Kbytes 页数：20 Pages

TI

德州仪器

丝印：SN54LS73AJ；Package：CDIP；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

文件：810.42 Kbytes 页数：20 Pages

TI

德州仪器

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes 页数：13 Pages

TI

德州仪器

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes 页数：17 Pages

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per f

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