4 x 4 REGISTER FILE OPEN-COLLECTOR

4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL /MSI SN54 /74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to conn

文件：107.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉

4 x 4 REGISTER FILE OPEN-COLLECTOR

4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL /MSI SN54 /74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to conn

文件：107.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

4-BIT D-TYPE REGISTERWITH 3-STATE OUTPUTS The SN54/74LS173A is a high-speed 4-BitRegister featuring 3-state outputs foruse in bus-organized systems. The clock is fully edge-triggered allowingeither a load from the D inputs ora hold (retain register contents) dependingon the state of the Input E

文件：207.6 Kbytes 页数：6 Pages

Motorola

摩托罗拉

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 页数：19 Pages

TI

德州仪器

丝印：SN54LS173AJ；Package：CDIP；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 页数：19 Pages

TI

德州仪器

丝印：SN54LS173AJ；Package：CDIP；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 页数：19 Pages

TI

德州仪器

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

4-BIT D-TYPE REGISTERWITH 3-STATE OUTPUTS The SN54/74LS173A is a high-speed 4-BitRegister featuring 3-state outputs foruse in bus-organized systems. The clock is fully edge-triggered allowingeither a load from the D inputs ora hold (retain register contents) dependingon the state of the Input E

文件：207.6 Kbytes 页数：6 Pages

Motorola

摩托罗拉

HEX D FLIP-FLOP

The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flo

文件：75.8 Kbytes 页数：3 Pages

Motorola

摩托罗拉

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

HEX D FLIP-FLOP

The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flo

文件：75.8 Kbytes 页数：3 Pages

Motorola

摩托罗拉