丝印：SN54LS109AJ；Package：CDIP；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

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德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件：596.77 Kbytes 页数：11 Pages

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德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件：271.36 Kbytes 页数：7 Pages

TI

德州仪器

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by

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