DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

文件：259.97 Kbytes 页数：6 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

文件：259.97 Kbytes 页数：6 Pages

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

文件：140.23 Kbytes 页数：4 Pages

Motorola

摩托罗拉

Dual JK Edge-Triggered Flip-Flop

文件：98.04 Kbytes 页数：6 Pages

NSC

国半

Dual JK Edge-Triggered Flip-Flop

文件：98.04 Kbytes 页数：6 Pages

NSC

国半

Dual JK Edge-Triggered Flip-Flop

文件：98.04 Kbytes 页数：6 Pages

NSC

国半