TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY

文件：45.24 Kbytes 页数：2 Pages

Motorola

摩托罗拉

TRIPLE 3-INPUT POSITIVE-AND GATES

文件：179.08 Kbytes 页数：7 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件：153.88 Kbytes 页数：5 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件：1.096 Mbytes 页数：17 Pages

TI

德州仪器

军用 3 通道、3 输入、4.5V 至 5.5V 双极与门

These devices contain three independent 3-input AND gates. The SN54LS11 and SN54S11 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS11 and SN74S11 are characterized for operation from 0°C to 70°C. • Package Options Include Plastic \"Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

文件：140.23 Kbytes 页数：4 Pages

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

文件：88.56 Kbytes 页数：3 Pages

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

文件：140.23 Kbytes 页数：4 Pages

Motorola

摩托罗拉