SMJ320C6701-SP中文资料航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装数据手册TI规格书

描述 Description

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

特性 Features

• Rad-Tolerant: 100-kRad (Si) TID
• QML-V Qualified, SMD 5962-98661
• 7-ns Instruction Cycle Time
• Eight 32-Bit Instructions/Cycle
• Pin Compatible With ’C6201 Fixed-Point DSP
• SMJ: QML Processing to MIL-PRF-38535
• Operating Temperature Ranges
• –55°C to 125°C
• VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core
• Four ALUs (Floating and Fixed Point)
• Two Multipliers (Floating and Fixed Point)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• All Instructions Conditional
• Instruction Set Features
• Hardware Support for IEEE Double-Precision Instructions
• 32-Bit Address Range
• Saturation
• Bit Counting
• 1M-Bit On-Chip SRAM
• 512K-Bit Dual-Access Internal Data (64K Bytes)
• 32-Bit External Memory Interface (EMIF)
• Glueless Interface to Asynchronous Memories: SRAM and EPROM
• Four-Channel Bootloading Direct Memory Access (DMA) Controller With Auxiliary Channel
• Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
• ST Bus Switching Compatible
• AC97 Compatible
• Two 32-Bit General-Purpose Timers
• IEEE Std 1149.1 (JTAG
• 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and Ceramic Land Grid Array (CLGA/ZMB) Package Types
• CMOS Technology
• 3.3-V I/Os, 1.9 V Internal
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• These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.