Si5510D数据手册Skyworks中文资料规格书

描述 Description

The Si5510D Wireless Jitter Attenuator Clock utilizes fifth-generation DSPLL® and MultiSynth™ technologies is optimized for enhanced Common Public Radio Interface (eCPRI) and CPRI wireless applications which demand the highest level of integration, low phase noise performance and power consumption. This highly integrated solution requires no external loop filter components and provides superior performance that is highly immune to external board disturbances such as power supply noise.



The Si5510D DSPLL bandwidth is digitally programmable to values from 10Hz to 4kHz. With phase noise of –145 dBc/Hz at 800 kHz offset for a 491.52 MHz carrier frequency and phase jitter as low as 47 fs RMS, the Si5510D accepts 4/6 inputs clock ranging from 8kHz to 1000 MHz differential and 8kHz to 250MHz for CMOS. Si5510D supports MultiSynch DCO and generates up to 18 clock outputs supporting JESD204B/C clock generation that are configurable in any combination of DCLK, SYSREF or as other system clocks. Each output supports delay/skew adjust and frequencies ranging from PP2S/PPS, 8kHz up to 3200MHz.



NXP’s 5G-NR Reference platform includes a Network Listen Mode (NLM) solution which incorporates the Si5510D clock as part of the hardware design and is supported by NXP’s software package. Customers should contact NXP for their 5G-NR Reference platform evaluation kits, documentation and software and Skyworks for the Si5510D.