Embedded Arrays

• High-density integration (0.25 µm CMOS process technology and 3/4/5-layer interconnect process, number of raw gates: 2,500,000 Max.)\r\n• High-speed operation (Internal gate delay: 107 ps/2.5 V, 2-input power NAND Typ.)\r\n• Selectable supply voltage: Operation on a single power supply (2.0 V, 2.5;

Epson

爱普生

CMOS Gate Arrays

Epson

爱普生