RTL8204B-VC-GR数据手册Realtek中文资料规格书

描述 Description

The RTL8204B-VC-GR is a single-chip highly integrated 5-port, 10Base-T/100Base-TX Ethernet transceiver implemented in 0.16µm CMOS technology. It is currently the world’s smallest 5-PHY chip package. Flexible hardware settings are provided to configure the various operating modes of the chip.
The RTL8204B-VC-GR provides 5 separate and independent channels. Each channel consists of a SMII/SS-SMII interface-to-MAC controller, and hardware pins are used to configure the interface for SMII, or SS-SMII mode.
A PECL (Pseudo Emitter Coupled Logic) receiver accepts input from a transceiver and directly passes it to a clock recovery circuit for data/clock recovery. The chip utilizes an advanced CMOS process to meet low voltage and low power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides excellent performance under all operating conditions.
A built-in UTP cable tester diagnoses an open/short fault in an attached cable. The RTL8204B-VC-GR also features very low power consumption. Additionally, pin-outs are designed to provide optimized direct routing, which simplifies the layout work and reduces possible EMI noise.

特性 Features

Supports 5-port integrated physical layer and transceiver for 10Base-T and 100Base-TX
Robust baseline wander correction for improved 100Base-TX performance
Complies with IEEE 802.3/802.3u
IEEE 802.3u compliant auto negotiation for 10/100Mbps control
Hardware controlled Flow control advertisement ability
Supports SMII/SS-SMII interfaces
Very low power consumption
Supports two power reduction methods:

Power saving mode (cable detection)
Power down mode
Power-on auto reset function eliminates the need for external reset circuits
Crossover detection and auto correction
Polarity detection and Auto Correction
Flexible serial/scan LED display modes
Cable tester for diagnosing open/short faults in attached cables
Supports 125MHz clock output
128-pin QFP package
1.8V/3.3V or 1.8V/2.5V power supply
0.16µm, CMOS technology

应用 Application

5 PHY for Fast Ethernet switch with twisted pair interface