RTL8201BL中文资料Single-Port 10/100M Fast Ethernet PHYceiver数据手册Realtek规格书

描述 Description

The RTL8201BL is a single-port PHYceiver with an MII (Media Independent Interface). It implements all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10Base-Tx Encoder/Decoder and Twisted Pair Media Access Unit (TPMAU). A PECL interface is supported to connect with an external 100Base-FX fiber optical transceiver. The chip is fabricated with an advanced CMOS process to meet low voltage and low power requirements.
The RTL8201BL can be used as a Network Interface Adapter, MAU, CNR, ACR, Ethernet Hub and Ethernet Switch. Additionally, it can be used in any embedded system with an Ethernet MAC that needs a twisted pair physical connection or fiber PECL interface to external 100Base-FX optical transceiver module.

特性 Features

Supports MII interface
Supports 7-wire SNI (Serial Network Interface)
Supports 10/100Mbps operation
Supports half/full duplex operation
Support of twisted pair or Fiber mode output
IEEE 802.3/802.3u compliant
Supports IEEE 802.3u clause 28 auto negotiation
Supports power down mode
Supports operation under Link Down Power Saving mode
Supports Base Line Winder (BLW) compensation
Supports repeater mode
Speed/duplex/auto negotiation adjustable
Utilizes DSP technology
3.3V operation with 5V IO signal tolerance
Low operation power consumption
Low power and dual supply 3.3V and 2.5V can be supported by the internal regulator function in conjunction with external power PNP transistor
Adaptive Equalization
25MHz crystal/oscillator as clock source
Fiber PECL interface support
Multiple network status LED support
Flow control ability support to co-work with MAC (by MDC/MDIO)
0.25µ CMOS process
48-pin LQFP package

应用 Application

Network interface adapters and Ethernet hubs/switches
Ethernet MAC-embedded systems that need twisted-pair physical connection, such as those for ADSL/cable modem routers and IA gateways