36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

Features
Power Supply  1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
Clock  Fast clock cycle time for high bandwidth  Two input clocks (K and /K) for precise DDR timing at clock rising edges only  Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems 

文件：399.71 Kbytes 页数：31 Pages

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36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

文件：896.89 Kbytes 页数：31 Pages

RENESAS

瑞萨

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

文件：896.89 Kbytes 页数：31 Pages

RENESAS

瑞萨

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

文件：896.89 Kbytes 页数：31 Pages

RENESAS

瑞萨

Memory

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瑞萨