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RM5261A中文资料PMC数据手册PDF规格书

RM5261A
厂商型号

RM5261A

功能描述

RM5261A??Microprocessor with 64-Bit System Bus Data Sheet Preliminary

文件大小

683.05 Kbytes

页面数量

42

生产厂商 PMC-Sierra, Inc
企业简称

PMC

中文名称

PMC-Sierra, Inc官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-2 11:10:00

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RM5261A价格和库存,欢迎联系客服免费人工找货

RM5261A规格书详情

Hardware Overview

The RM5261A offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5261A are briefly described below.

特性 Features

• Dual Issue superscalar microprocessor

• 250, 300, and 350 MHz operating frequencies

• Up to 420 Dhrystone 2.1 MIPS

• High-performance system interface

• 64-bit multiplexed system address/data bus for optimum price/performance

• High-performance write protocols maximize uncached write bandwidth

• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

• IEEE 1149.1 JTAG boundary scan

• Integrated on-chip caches

• 32 KB instruction and 32 KB data — 2 way set associative

• Per set locking

• Virtually indexed, physically tagged

• Write-back and write-through on a per page basis

• Pipeline restart on first doubleword for data cache misses

• Integrated memory management unit

• Fully associative joint TLB (shared by I and D translations)

• 48 dual entries map 96 pages

• Variable page size (4 KB to 16 MB in 4x increments)

• High-performance floating-point unit: up to 700 MFLOPS

• Single cycle repeat rate for common single-precision operations and some double-precision operations

• Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations

• Single cycle repeat rate for single-precision combined multiply-add operation

• MIPS IV instruction set

• Floating point multiply-add instruction increases performance in signal processing and graphics applications

• Conditional moves to reduce branch frequency

• Index address modes (register + register)

• Embedded application enhancements

• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction

• I and D cache locking by set

• Optional dedicated exception vector for interrupts

• Fully static 0.18 micron CMOS design with power down logic

• Standby reduced power mode with WAIT instruction

• 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O

• 208-pin QFP package

产品属性

  • 型号:

    RM5261A

  • 制造商:

    PMC

  • 制造商全称:

    PMC

  • 功能描述:

    64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus

供应商 型号 品牌 批号 封装 库存 备注 价格
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23+
QFP208
3000
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1
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2317
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2447
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100500
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1923+
QFP208
2000
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23+
PQFP
50000
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3600
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3000
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