RM5261-266-Q中文资料PMC数据手册PDF规格书

Hardware Overview

The RM5261 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5261 are briefly described below

Features

• Dual Issue superscalar microprocessor

• 200, 250, 266 MHz operating frequencies

• 320 Dhrystone 2.1 MIPS

• High-performance system interface

• 64-bit multiplexed system address/data bus for optimum price/performance

• High-performance write protocols maximize uncached write bandwidth

• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

• IEEE 1149.1 JTAG boundary scan

• Integrated on-chip caches

• 32KB instruction and 32KB data — 2 way set associative

• Virtually indexed, physically tagged

• Write-back and write-through on a per page basis

• Pipeline restart on first doubleword for data cache misses

• Integrated memory management unit

• Fully associative joint TLB (shared by I and D translations)

• 48 dual entries map 96 pages

• Variable page size (4 KB to 16 MB in 4x increments)

• High-performance floating-point unit: up to 530 MFLOPS

• Single cycle repeat rate for common single-precision operations and some double-precision operations

• Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations

• Single cycle repeat rate for single-precision combined multiply-add operation

• MIPS IV instruction set

• Floating point multiply-add instruction increases performance in signal processing and graphics applications

• Conditional moves to reduce branch frequency

• Index address modes (register + register)

• Embedded application enhancements

• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction

• I and D cache locking by set

• Optional dedicated exception vector for interrupts

• Fully static 0.25 micron CMOS design with power down logic

• Standby reduced power mode with WAIT instruction

• 2.5 V core with 3.3 V IOs

• 208-pin PQFP package