RHFLVDS217数据手册ST中文资料规格书

描述 Description

The RHFLVDS217 serializer converts 21 bits of CMOS/TTL data into three LVDS (low voltage differential signaling) data streams. A phase-locked transmitter clock is transmitted in parallel with the data streams over a fourth LVDS link. With every cycle of the transmitter clock, 21 bits of input data are sampled and transmitted.
At a transmitter clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/s).
The RHFLVDS217 serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.
All pins have cold spare buffers. These buffers are high impedance when VCC is tied to 0 V.

特性 Features

• 15 to 75 MHz shift clock support
• Fail-safe function
• 8 kV HBM on LVDS pins
• Power-down mode
• Up to 197 Mbytes/s bandwidth
• 325 mV (typ.) LVDS swing
• PLL requires no external components
• Rising edge strobe
• Operational environment: total dose irradiation testing to MIL-STD-883 method 1019
• Total dose: 300 krad (Si)
• Latch-up immune (LET > 120 MeV-cm2/mg)
• Compatible with ANSI/TIA/EIA-644 standard