Features

▪ Six independent timing channels

• Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

• Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

• Each FOD supports output phase tuning with 1ps

▪ 12 differential / 24 LVCMOS outputs

• Any frequency from 0.5Hz to 1GHz (250MHz for LVCMOS)

• Jitter below 150fs RMS (10kHz to 20MHz)

• Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL,

and HSTL output modes

• Differential output swing is selectable: 400mV / 650mV /

800mV / 910mV

• Independent output voltages of 3.3V, 2.5V, or 1.8V

▪ LVCMOS additionally supports 1.5V or 1.2V swings

• The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

▪ 5 differential / 10 single-ended clock inputs

• Supports any frequency from 0.5Hz to 1GHz

• Any input can be mapped to any or all of the timing channels

• Redundant inputs frequency independent of each other

• Any input can be designated as external frame/sync pulse of

EPPS (even pulse per second), 1PPS (Pulse per Second),

5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

• Per-input programmable phase offset of up to ±1.638s in

1ps steps

▪ Three GPIOs can be configured as single-ended clock inputs

supporting frequencies from 0.5Hz to 150MHz

▪ Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring, and/or LOS input pins

• Loss of Signal (LOS) input pins (via GPIOs) can be assigned

to any input clock reference

▪ Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive / non-revertive, and other

programmable settings

▪ System APLL operates from fundamental-mode crystal: 25MHz

to 54MHz or from a crystal oscillator

▪ System DPLL accepts an XO, TCXO, or OCXO operating at

virtually any frequency from 1MHz to 150MHz

▪ DPLLs can be configured as DCOs to synthesize Precision

Time Protocol (PTP) / IEEE 1588 clocks

• DCOs generate PTP based clocks with frequency resolution

less than 1.11 × 10-16

▪ DPLL Phase detectors can be used as Time-to-Digital

Converters (TDC) with precision below 1ps

• TDCs are readable at periods from 1ms to 100s

▪ DPLL Digital Loop Filters (DLFs) are programmable with cut off

frequencies from 0.09mHz to 12kHz

• DPLL architecture supports the use of external DLFs

implemented in software

▪ DPLL/DCO channels share frequency information using the

Combo Bus to simplify compliance with ITU-T G.8273.2

▪ Switching between DPLL and DCO modes is hitless and

dynamic

▪ Supports 1MHz I2

C or 50MHz SPI serial processor ports

▪ Can configure itself automatically after reset via:

• Internal customer-definable One-Time Programmable (OTP)

memory with up to 16 different configurations

• Standard external I2C EEPROM is serial port in I2C mode

▪ 1149.1 JTAG Boundary Scan

▪ 10 × 10 × 0.9 mm 72-QFN package