FemtoClock®2 Sub-100fs Universal Frequency Translator

Features • Jitter below 100fs RMS maximum (10kHz to 20MHz) • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL) ○ Operates from an integrated 60MHz crystal ○ APLL frequency independent of input / crystal frequency ○ Operates

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瑞萨

FemtoClock®2 Jitter Attenuator or Clock Generator

The RC32514A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32514A can act as a frequency synthesizer to locally generate the reference clock, a jit • Jitter below 100fs RMS (10kHz to 20MHz)\n• PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)• Operates from an internal crystal\n• Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally;

Renesas

瑞萨

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上传：富凯科技(深圳）有限公司

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上传：深圳市坤融电子科技有限公司

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上传：深圳市坤融电子科技有限公司