VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

FemtoClock Clock Generator

Features ▪ Low power, less than 1.4W typical ▪ Low jitter, less than 100 fs-RMS ▪ PCIe Gen 1-6 CC, SRIS, and SRNS support ▪ Up to six fractional output dividers and 12 integer output dividers • Each fractional output divider is free-run and locked to APLL ▪ Each fractional output divider c

文件：2.60276 Mbytes 页数：48 Pages

RENESAS

瑞萨

EmbeddedModem Family

The new Conexant RC224ATL utilizes a new integrated data pump/controller to allow the device to directly connect to host processors that are 3.3 V I/O capable. The codec used in the new part is the same as the codec used in the existing RC224ATL. The new device is form, fit, and function compatibl

文件：1.12043 Mbytes 页数：104 Pages

CONEXANT

EmbeddedModem Family

The new Conexant RC224ATL utilizes a new integrated data pump/controller to allow the device to directly connect to host processors that are 3.3 V I/O capable. The codec used in the new part is the same as the codec used in the existing RC224ATL. The new device is form, fit, and function compatibl

文件：1.12043 Mbytes 页数：104 Pages

CONEXANT