RC19004数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The RC19004 is a 4-output PCIe Gen6 buffer that is backward compatible to earlier PCIe generations. The RC19004 provides ultra-low additive jitter and reduced in-to-out delay performance for better design-margin and incorporates several features for easier and more robust design.

特性 Features

• LP-HCSL outputs eliminate up to 16 terminated resistors
• PCIe Gen 1–6 compliance
• Drive both source-terminated and double-terminated loads
• Selectable output slew rate via pin
• Support both 85Ω and 100Ω output impedance versions
• Open-drain LOS (Loss-Of-Signal) indication output
• Power down tolerance (PDT)
• Flexible startup sequencing (FSS)
• Automatic clock parking (ACP)
• Dedicated OE# pins to control group output
• 4-wire Side-Band interface and device daisy-chaining 
• SMBus write protection features with 9 selectable addresses
• 4 × 4 mm 28-VFQFPN package

应用 Application

• Intel Xeon CPU服务器解决方案