丝印：PT；Package：DO-214AC；5.0 To 200V 600W Surface Mount Transient Voltage Suppressors (TVS)

Glass passivated chip 600W peak pulse power capability with a 10/1000us waveform Repetitive rate (duty cycle):0.01 Typical IR less than 1μA above 10V Excellent clamping capability Very fast response time High temperature soldering: 260°C/10s at terminals. RoHS compliant Features

文件：3.35089 Mbytes 页数：6 Pages

UNSEMI

优恩半导体

丝印：pT；Package：SOT886；Low-power D-type flip-flop; positive-edge trigger

1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger act

文件：295 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT1115；Low-power D-type flip-flop; positive-edge trigger

1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger act

文件：295 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT1202；Low-power D-type flip-flop; positive-edge trigger

1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger act

文件：295 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT353-1；Low-power D-type flip-flop; positive-edge trigger

1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger act

文件：295 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT1226-3；Low-power D-type flip-flop; positive-edge trigger

1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger act

文件：295 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT1116；Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

文件：279.64 Kbytes 页数：19 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：pT；Package：SOT1203；Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

文件：279.64 Kbytes 页数：19 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：PT；Package：SOT-23-3；ULTRA LOW QUIESCENT CURRENT CMOS LDO

Features - Ultra-Low Quiescent Current: 1.0μA Typical - Output Voltages: 1.2V, 1.4V, 1.5V, 1.8V, 2.1V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V, 3.6V and 4.0V - High Output Voltage Accuracy: ±2 - Output Current: 250mA - Low Dropout Voltage: - 25mV Typical at IOUT = 10mA and VOUT = 3V - 200mV Typical a

文件：780.53 Kbytes 页数：29 Pages

DIODES

美台半导体

丝印：PT；Package：SSOP5；Voltage Detector IC Adjustable Output Delay

Silicon Monolithic Integrated Circuit Featues 1. Detection voltage lineup : 2.3 ~ 6.0V 2. High precision detection voltage : +- 1.0.

文件：316.57 Kbytes 页数：6 Pages

ROHM

罗姆