PLS159中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs.

FEATURES

• High-speed version of PLS159

• fMAX = 18MHz

– 25MHz clock rate

• Field-Programmable (Ni-Cr link)

• 4 dedicated inputs

• 13 control gates

• 32 AND gates

• 21 OR gates

• 45 product terms:

– 32 logic terms

– 13 control terms

• 4 bidirectional I/O lines

• 8 bidirectional registers

• J-K, T, or D-type flip-flops

• Power-on reset feature on all flip-flops (Fn = 1)

• Asynchronous Preset/Reset

• Complement Array

• Active-High or -Low outputs

• Programmable OE control

• Positive edge-triggered clock

• Input loading: –100µA (max.)

• Power dissipation: 750mW (typ.)

• TTL compatible

• 3-State outputs

APPLICATIONS

• Random sequential logic

• Synchronous up/down counters

• Shift registers

• Bidirectional data buffers

• Timing function generators

• System controllers/synchronizers

• Priority encoder/registers