Programmable logic sequencer 16 횞 45 횞 12

DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunctio

文件：132.84 Kbytes 页数：12 Pages

PHI

飞利浦

Programmable logic sequencer 16 × 45 × 12

恩XP

恩智浦

Programmable logic sequencer 16 횞 45 횞 12

DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunctio

文件：132.84 Kbytes 页数：12 Pages

PHI

飞利浦

Programmable logic sequencer 16 횞 45 횞 12

DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunctio

文件：132.84 Kbytes 页数：12 Pages

PHI

飞利浦

Programmable logic sequencer 16 횞 45 횞 12

DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunctio

文件：132.84 Kbytes 页数：12 Pages

PHI

飞利浦