Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

文件：166.6 Kbytes 页数：10 Pages

PLL

Programmable DDR Zero Delay Clock Driver

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

文件：166.6 Kbytes 页数：10 Pages

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

文件：166.6 Kbytes 页数：10 Pages

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

文件：166.6 Kbytes 页数：10 Pages

PLL