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PLL102-05SCL-R中文资料PDF规格书
PLL102-05SCL-R规格书详情
DESCRIPTION
The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
• Frequency range 25 ~ 60MHz.
• Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
• Less than 150 ps cycle - cycle jitter.
• Output Enable function tri-state outputs.
• 3.3V operation.
• Available in 8-Pin 150mil SOIC.
产品属性
- 型号:
PLL102-05SCL-R
- 制造商:
PLL
- 制造商全称:
PLL
- 功能描述:
Low Skew Output Buffer
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Phaseli |
23+ |
SOIC8 |
8560 |
受权代理!全新原装现货特价热卖! |
询价 | ||
PHASELINK |
22+ |
SSOP |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
询价 | ||
3000 |
公司存货 |
询价 | |||||
16+ |
FBGA |
4000 |
进口原装现货/价格优势! |
询价 | |||
PHASELINK |
22+ |
SOIC8 |
5000 |
全新原装现货!自家库存! |
询价 | ||
Phaselink |
589220 |
16余年资质 绝对原盒原盘 更多数量 |
询价 | ||||
A/N |
1715+ |
SOP |
251156 |
只做原装正品现货假一赔十! |
询价 | ||
PHASELIN |
0350+ |
SSOP48 |
30 |
普通 |
询价 | ||
只做原装 |
21+ |
SOP-8 |
36520 |
一级代理/放心采购 |
询价 | ||
Phaselink |
23+ |
SOIC8 |
12800 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
询价 |