PI6C2510-133中文资料Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs数据手册Diodes规格书

描述 Description

The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable.
This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.

特性 Features

• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
   meets 133 MHz Registered DIMM Synchronous DRAM
   modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
   for EMI reduction
• Zero Input-to-Output delay: Distribute one Clock Input
   to one Bank of Ten outputs, with an output enable.
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
   for low noise and EMI reduction
• Operates at 3.3V VCC
• Packaging(Pb-free & Green available):
   - 24-pin TSSOP (L)

应用 Application

• Allows Clock Input to have Spread Spectrum modulation
   for EMI reduction
• Zero Input-to-Output delay: Distribute one Clock Input
   to one Bank of Ten outputs, with an output enable.
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
   for low noise and EMI reduction
• Operates at 3.3V VCC
• Packaging(Pb-free & Green available):
   - 24-pin TSSOP (L)

简介

PI6C2510-133属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PI6C2510-133时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。