Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to

文件：141.17 Kbytes 页数：5 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description\nThe PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to an • Operating Frequency up to 150 MHz\n• Low-Noise Phase-Locked Loop Clock Distribution that\n   meets 133 MHz Registered DIMM Synchronous DRAM\n   modules for server/workstation/PC applications\n• Allows Clock Input to have Spread Spectrum modulation\n   for EMI reduction\n• Zero Input-to-Output dela;

Diodes

美台半导体

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input

文件：331.65 Kbytes 页数：4 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input

文件：331.65 Kbytes 页数：4 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input

文件：331.65 Kbytes 页数：4 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description\nThe PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to an • Operating Frequency up to 150 MHz\n• Low-Noise Phase-Locked Loop Clock Distribution that\n   meets 133 MHz Registered DIMM Synchronous DRAM\n   modules for server/workstation/PC applications\n• Allows Clock Input to have Spread Spectrum modulation\n   for EMI reduction\n• Zero Input-to-Output dela;

Diodes

美台半导体

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DVR 10OUT 24-TSSOP

DIODES

美台半导体

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DVR 10OUT 24-TSSOP

DIODES

美台半导体

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DVR 10OUT 24-TSSOP

DIODES

美台半导体