丝印：PCI2050BPDV；Package：LQFP；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

丝印：PCI2050BPDV；Package：LQFP；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

丝印：PCI2050BZWT；Package：NFBGA；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

丝印：PCI2050BZWT；Package：NFBGA；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

Up to 16 Inputs with Vertical Connectors

文件：200.91 Kbytes 页数：1 Pages

ADL

Periphelar Coupled Input NPN

文件：291.15 Kbytes 页数：34 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

Series Specification

文件：507.03 Kbytes 页数：4 Pages

LEIDITECH

雷卯电子

Series Specification

文件：507.03 Kbytes 页数：4 Pages

LEIDITECH

雷卯电子