PCA9512ADP数据手册恩XP中文资料规格书

描述 Description

The PCA9512A/B is a hot swappable I²C-bus and SMBus buffer that allows I/O cardinsertion into a live backplane without corruption of the data and clock buses and includestwo dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systemswhile maintaining the best noise margin for each voltage level. Either pin may be poweredwith supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supplyvoltage is higher. Control circuitry prevents the backplane from being connected to thecard until a stop bit or bus idle occurs on the backplane without bus contention on thecard. When the connection is made, the PCA9512A/B provides bidirectional buffering,keeping the backplane and card capacitances isolated.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated13 Dec 2010), so the PCA9512B will be discontinued in the near future and is notrecommended for new designs.
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-upcurrents while still meeting rise time requirements. The PCA9512A/B incorporates a digitalinput pin that enables and disables the rise time accelerators on all four SDAn and SCLnpins.
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V tominimize the current required to charge the parasitic capacitance of the chip.
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allowsthem to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or inparallel and to the I²C compliant side of static offset bus buffers, but not to the static offsetside of those bus buffers.

特性 Features

Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ΔV/Δt rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same
5 V to 3.3 V level translation with optimum noise margin
High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V
1 V precharge on all SDAn and SCLn pins
Supports clock stretching and multiple master arbitration and synchronization
Operating power supply voltage range: 2.7 V to 5.5 V
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8)

应用 Application

cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system