PCA9505DGG中文资料40-bit I2C-bus I/O port with RESET, OE and INT数据手册恩XP规格书

描述 Description

The PCA9505/PCA9506 provide 40-bit parallel input/output (I/O) port expansion for I²C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sourcing 10 mA and sinking 15 mA with a total package load of 600 mA to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. Output ports are totem-pole and their logic state changes at the Acknowledge (bank change). The PCA9505 is identical to the PCA9506 except that it includes 100 kΩ internal pull-up resistors on all the I/Os. The PCA9506 does not include the internal pull-ups on the I/Os to reduce power consumption when used as outputs or when the input is driven by a push-pull driver.
The device can be configured to have each input port to be masked in order to prevent it from generating interrupts when its state changes and to have the I/O data logic state to be inverted when read by the system master.
An open-drain interrupt (INT) output pin allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable (OE) pin 3-states any I/O selected as an output and can be used as an input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os as inputs. Three address select pins configure one of 8 slave addresses.
The PCA9506 is available in 56-pin TSSOP and HVQFN packages, while the PCA9505 is available only in a TSSOP package. They are both specified over the -40 Cel to +85 Cel industrial temperature range.

特性 Features

Standard mode (100 kHz) and Fast mode (400 kHz) compatible I²C-bus serial interface
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
40 configurable I/O pins that default to inputs at power-up
PCA9505 includes 100 kΩ internal pull-up resistors on all the I/Os
Outputs: Totem-pole (10 mA source, 15 mA sink) with controlled edge rate output structure
Active LOW output enable (OE) input pin 3-states alloutputs
Output state change on Acknowledge
Open-drain active LOW interrupt (INT) output pin allowsmonitoring of logic level change of pins programmed as inputs
Inputs: Programmable Interrupt Mask Control for input pins that do not require an interruptwhen their states change
Polarity Inversion register allows inversion of the polarity of the I/O pins whenread
Active LOW reset (RESET) input pin resets device to power-updefault state
3 programmable address pins allowing 8 devices on the same bus
Designed for live insertion Minimize line disturbance (IOFF and power-up 3-state)
Signal transient rejection (50 ns noise filter and robust I²C-bus state machine)
Low standby current
-40 Cel to +85 Cel operation
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 VCDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA
Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages

应用 Application

Servers
RAID systems
Industrial control
Medical equipment
PLCs
Cell phones
Gaming machines
Instrumentation and test measurement