8-bit microcontroller with accelerated two-clock 80C51 core 8 kB Flash with 512-byte data EEPROM and 768-byte RAM

文件：291.92 Kbytes 页数：60 Pages

PHI

飞利浦

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB Flash with 512-byte data EEPROM and 768-byte RAM

文件：291.92 Kbytes 页数：60 Pages

PHI

飞利浦

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

OverviewThe P89LPC9321 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89L \n\n2.1 Principal features\n\n\n\n•8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n\n•256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.\n\n•512-byte customer data EEPROM ;

恩XP

恩智浦

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

General description\nThe P89LPC9321 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated Principal features\n■ 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.\n   Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n■ 256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.\n■ 512-byte customer data EEPROM on-chip all;

恩XP

恩智浦

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

Overview The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P8 Principal features\n8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-bytepages. Single-byte erasing allows any byte(s) to be used as non-volatile datastorage.\n256-byte RAM data memory, 512-byte auxiliary on-chip RAM.\n512-byte customer data EEPROM on chip allows serialization;

恩XP

恩智浦