P89LPC932A1FDH中文资料8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM数据手册恩XP规格书

描述 Description

Overview The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC932A1 in order to reduce component count, board space, and system cost.

特性 Features

Principal features
8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-bytepages. Single-byte erasing allows any byte(s) to be used as non-volatile datastorage.
256-byte RAM data memory, 512-byte auxiliary on-chip RAM.
512-byte customer data EEPROM on chip allows serialization of devices, storageof set-up parameters, etc.
Two analog comparators with selectable inputs and reference source.
Two 16-bit counter/timers (each may be configured to toggle a port output upontimer overflow or to become a PWM output) and a 23-bit system timer that canalso be used as a RTC.
Enhanced UART with fractional baud rate generator, break detect, framing errordetection, and automatic address detection; 400 kHz byte-wide I²C-buscommunication port and SPI communication port.
CCU provides PWM, input capture, and output compare functions.
High-accuracy internal RC oscillator option allows operation without externaloscillator components. The RC oscillator option is selectable and finetunable.
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may bepulled up or driven to 5.5 V).
28-pin TSSOP, PLCC, HVQFN, and DIP packages with 23 I/O pins minimum and up to26 I/O pins while using on-chip oscillator and reset options.
Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222ns for all instructions except multiply and divide when executing at 18 MHz.This is six times the performance of the standard 80C51 running at the sameclock frequency. A lower clock frequency for the same performance results inpower savings and reduced EMI.
In-Circuit Programming (ICP) allows simple production coding with commercialEPROM programmers. Flash security bits prevent reading of sensitive applicationprograms.
Serial flash In-System Programming (ISP) allows coding while the device ismounted in the end application.
In-Application Programming (IAP) of the flash code memory. This allows changingthe code in a running application.
Watchdog timer with separate on-chip oscillator, requiring no externalcomponents. The watchdog prescaler is selectable from eight values.
Low voltage reset (brownout detect) allows a graceful system shutdown when powerfails. May optionally be configured as an interrupt.
Idle and two different power-down reduced power modes. Improved wake-up fromPower-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1 uA (total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external resetcomponents. A reset counter and reset glitch suppression circuitry preventspurious and incomplete resets. A software reset function is alsoavailable.
Configurable on-chip oscillator with frequency range options selected by userprogrammed flash configuration bits. Oscillator options support frequencies from20 kHz to the maximum operating frequency of 18 MHz.
Oscillator fail detect. The watchdog timer has a separate fully on-chiposcillator allowing it to perform an oscillator fail detect function.
Programmable port output configuration options: quasi-bidirectional, open drain,push-pull, input-only.
Port 'input pattern match' detect. Port 0 may generate an interrupt when thevalue of the pins match or do not match a programmable pattern.
LED drive capability (20 mA) on all port pins. A maximum limit is specified forthe entire chip.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns minimum ramp times.
Only power and ground connections are required to operate the P89LPC932A1 wheninternal reset option is selected.
Four interrupt priority levels.
Eight keypad interrupt inputs, plus two additional external interruptinputs.
Schmitt trigger port inputs.
Second data pointer.
Emulation support.
Comparison to the P89LPC932
The P89LPC932A1 includes several improvementscompared to the P89LPC932. Please see P89LPC932A1 User manual for additional detailedinformation.
Byte-erasability has been added to the user code memory space.
All of the errata described in the P89LPC932 Errata sheet have beenfixed.
Serial ICP has been added.
The RCCLK bit has been added to the TRIM register allowing the RCCLK to beselected as the CPU clock (CCLK) regardless of the settings in UCFG1, allowingthe internal RC oscillator to be selected as the CPU clock without the need toreset the device.
Enhancements added to the ISP/IAP code to improve code safety and increaseISP/IAP functionality. This may require slight changes to original P89LPC932code using IAP function calls. Some ISP/IAP settings are different than theoriginal P89LPC932. Tools designed to support the P89LPC932A1 should be used toprogram this device, such as Flash Magic version 1.98, or later.