P89LPC921FDH数据手册恩XP中文资料规格书

描述 Description

OverviewThe P89LPC920/921/922/9221 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC920/921/922/9221 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC920/921/922/9221 in order to reduce component count, board space, and system cost.

特性 Features

Principal features



•2 kB/4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable page size, and single byte erase.

•256-byte RAM data memory.

•Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output.

•Real-Time clock that can also be used as a system timer.

•Two analog comparators with selectable inputs and reference source.

•Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities.

•400 kHz byte-wide I²C-bus communication port.

•Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed Flash configuration bits). The RC oscillator (factory calibrated to +-1 pct) option allows operation without external oscillator components. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. The RC oscillator option is selectable and fine tunable.

•2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).

•High drive current (20 mA) on eight I/O pins on the P89LPC9221 (P0.3 to P0.7, P1.4, P1.6, P1.7).



Additional features



•15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset options.

•20-pin TSSOP and DIP packages.

•A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.

•In-Application Programming of the Flash code memory. This allows changing the code in a running application.

•Serial Flash programming allows simple in-circuit production coding. Flash security bits prevent reading of sensitive application programs.

•Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.

•Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.

•Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 uA (total Power-down with voltage comparators disabled).

•Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

•Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.

•Programmable port output configuration options:
•quasi-bidirectional,

•open drain,

•push-pull,

•input-only.




•Port 'input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.

•LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip (160 mA for the P89LPC9221; 80 mA for the P89LPC920/921/922).

•Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.

•Only power and ground connections are required to operate the P89LPC920/921/922/9221 when internal reset option is selected.

•Four interrupt priority levels.

•Eight keypad interrupt inputs, plus two additional external interrupt inputs.

•Second data pointer.

•Schmitt trigger port inputs.

•Emulation support.