P89LPC912HDH中文资料8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM数据手册恩XP规格书

描述 Description

OverviewThe P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost.

特性 Features

Principal features



•1 kB byte-erasable flash code memory organized into 256 B sectors and 16 B pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

•128 B RAM data memory.

•Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output.

•23-bit system timer that can also be used as a RTC.

•Two analog comparators with selectable inputs and reference source.

•Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC913, P89LPC914).

•SPI communication port.

•Internal RC oscillator (factory calibrated to +-1 pct) option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.

•2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).

•Up to 12 I/O pins when using internal oscillator and reset options.



Additional features



•14-pin TSSOP packages.

•A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz (167 ns to 333 ns at 12 MHz). This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.

•In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.

•Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.

•Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.

•Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.

•Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 uA (total power-down with voltage comparators disabled).

•Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

•Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz (P89LPC912, P89LPC913).

•Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.

•Programmable port output configuration options: quasi-bidirectional, open-drain, push-pull, input-only.

•Port 'input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.

•LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.

•Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.

•Only power and ground connections are required to operate the P89LPC912/913/914 when internal reset option is selected.

•Four interrupt priority levels.

•Four keypad interrupt inputs.

•Second data pointer.

•Schmitt trigger port inputs.

•Emulation support.