P89LPC9103FTK数据手册恩XP中文资料规格书

描述 Description

OverviewThe P89LPC9102/9103/9107 are single-chip microcontrollers in low-cost 10-pin and 14-pin packages based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9102/9103/9107 in order to reduce component count, board space, and system cost.

特性 Features

Principal features



•1 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

•128-byte RAM data memory.

•Two 16-bit timer/counters (P89LPC9102/9107). Two 16-bit timers (P89LPC9103)

•23-bit system timer that can also be used as a RTC.

•Four input multiplexed 8-bit A/D converter/single DAC output. One analog comparator with selectable reference.

•Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC9103/9107).

•High-accuracy internal RC oscillator option, factory calibrated to 1 pct, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.

•VDD operating range of 2.4 V to 3.6 V with 5 V tolerant I/O pins (may be pulled up or driven to 5.5 V).

•Up to 10 (P89LPC9107) or eight (P89LPC9102/9103) I/O pins when using internal oscillator and reset options.

•Ultra-small 10-pin HVSON package (P89LPC9102/9103). 14-pin TSSOP and DIP packages (P89LPC9107).



Additional features



•A high performance 80C51 CPU provides instruction cycle times of 136 ns to 272 ns for all instructions except multiply and divide when using the internal 7.3728 MHz RC oscillator in clock doubling mode (111 ns to 222 ns when using an external 18 MHz clock). A lower clock frequency for the same performance results in power savings and reduced EMI.

•In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.

•Serial flash ICP allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.

•Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.

•Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.

•Idle mode and two different reduced power Power-down modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical Power-down mode current is less than 1 uA (total Power-down mode with voltage comparators disabled).

•Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

•Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.

•Port 'input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.

•LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.

•Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.

•Only power and ground connections are required to operate the P89LPC9102/9103/9107 when internal reset option is selected.

•Four interrupt priority levels.

•Two keypad interrupt inputs.

•Second data pointer.

•External clock input.

•Clock output (P89LPC9102/9107).

•Schmitt trigger port inputs.

•Emulation support.