LBTP180D3T1G

Marking：P3；Package：DFN2020-3；PNP Silicon

LM2301M

Marking：P3；Package：SOT-723；P-Channel Enhancement Mode Power MOSFET

LMSZ5268BT1G

Marking：P3；Package：SOD-123；Zener Voltage Regulators 500 mW SOD??23 Surface Mount

LMT70.66P02K

Marking：P3；Package：SOT-723；P-Channel Enhancement Mode Power MOSFET

NC7WZ125L8X

Marking：P3；Package：MAC08A；TinyLogic
UHS Dual Buffer with 3-STATE Outputs

PESD9V0V4UK

Marking：P3；Package：SOT891；Very low capacitance unidirectional quadruple ESD protection diode arrays

6P30006ANLGI

Marking：P36AGI；Package：QFN；CLOCK DISTRIBUTION CIRCUIT

Features •Packagedin24-pinQFN •LVCMOSorTCXOsinewaveinput •+1.8Voperatingvoltage •Glitch-freeinputswitching •Eightbufferedsquarewaveoutputsat1.8VLVCMOS levels •IndividualoutputenablescontrolledviaI2CorOEx •Pbfree,RoHScompliantpackage •Industrialtemp

6P30006ANLGI8

Marking：P36AGI；Package：QFN；CLOCK DISTRIBUTION CIRCUIT

Features •Packagedin24-pinQFN •LVCMOSorTCXOsinewaveinput •+1.8Voperatingvoltage •Glitch-freeinputswitching •Eightbufferedsquarewaveoutputsat1.8VLVCMOS levels •IndividualoutputenablescontrolledviaI2CorOEx •Pbfree,RoHScompliantpackage •Industrialtemp

74AUP1T1326GT

Marking：p31；Package：SOT833-1；Low-power dual supply buffer/line driver; 3-state

1Generaldescription The74AUP1T1326isahigh-performance,low-power,low-voltage,single-bit,dualsupply buffer/linedriverwithoutputenablecircuitry. The74AUP1T1326isdesignedforlogic-leveltranslationapplicationsandcombinesthe functionsofthe74AUP1G32and74AUP1G126.Thebuf

74AUP2G32DC

Marking：p32；Package：SOT765-1；Low-power dual 2-input OR gate

1.Generaldescription The74AUP2G32isadual2-inputORgate.Schmitt-triggeractionatallinputsmakesthecircuit tolerantofslowerinputriseandfalltimes.Thisdeviceensuresverylowstaticanddynamicpower consumptionacrosstheentireVCCrangefrom0.8Vto3.6V.Thisdeviceis