OMAP3530-HIREL中文资料OMAP3530-HiRel 应用处理器数据手册TI规格书

描述 Description

OMAP3525 and OMAP3530 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture.
The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:
Streaming video 3D mobile gaming Video conferencing High-resolution still imageThe device supports high-level operating systems (OSs), such as:
Linux Windows CEThis OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.
The following subsystems are part of the device:
Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core POWERVR SGX™ subsystem for 3D graphics acceleration to support display and gaming effects (3530 only) Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripheralsThe device also offers:
A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex&trade adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption. Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)OMAP25 and OMAP3530 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package.
Table 1-1 lists the differences between the CBB, CBC, and CUS packages.

特性 Features

• OMAP325 and OMAP3530 Applications Processor:
• MPU Subsystem
• NEON™ SIMD Coprocessor
• Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
• POWERVR SGX™ Graphics Accelerator (OMAP3530 Device Only)
• Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
• Fine Grained Task Switching, Load Balancing, and Power Management
• Fully Software-Compatible With C64x and C64x and ARM9™
• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
• Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) perClock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
• 64 32-Bit General-Purpose Registers
• All Instructions Conditional
• Exceptions Support for Error Detection and Program Redirection
• C64x+ L1/L2 Memory Architecture
• 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
• 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
• 8-Bit Overflow Protection
• Normalization, Saturation. Bit-Counting
• Additional Instructions to Support Complex Multiplies
• Thumb®-2
• In-Order, Dual-Issue, Superscalar Microprocessor Core
• Over 2x Performance of ARMv6 SIMD
• Jazelle® RCT Execution Environment Architecture
• Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
• 16K-Byte Data Cache (4-Way Set-Associative)
• 112K-Byte ROM
• Endianess:
• ARM Data – Configurable
• External Memory Interfaces:
• Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
• General Purpose Memory Controller (GPMC)
• Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
• Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
• System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)
• Memory Data Input
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
• Preview Engine for Real-Time Image Processing
• Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
• Separate Horizontal/Vertical Control
• Display Subsystem
• HD Maximum Resolution
• Support for Remote Frame Buffer Interface (RFBI) LCD Panels
• Luma/Chroma Separate Video (S-Video)
• Resize Images From 1/4x to 8x
• 8-bit Alpha Blending
• 5K-Byte Transmit/Receive Buffer (McBSP2)
• Direct Interface to I2S and PCM Device and TDM Buses
• Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
• High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
• Supports Transceiverless Link Logic (TLL)
• Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
• Removable Media Interfaces:
• Comprehensive Power, Reset, and Clock Management
• Dynamic Voltage and Frequency Scaling (DVFS)
• Embedded Trace Macro Interface (ETM)
• 12 32-bit General Purpose Timers
• 1 32-bit 32-kHz Sync Timer
• 6 5-nm CMOS Technology
• Discrete Memory Interface (Not Available in CBC Package)
• 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
• 1.8-V I/O and 3.0-V (MMC1 only), 0.985-V to 1.35-V Adaptive Processor Core Voltage 0.985-V to 1.25-V Adaptive Core Logic Voltage Note: thee are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex™ AVS.
• Portable Media Player
• Digital TV
• Portable Data Collection
• Gaming
• Smart White Goods
• Ultra Mobile Devices

POWERVR SGX is a trademark of Imagination Technologies Ltd. OMAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.