OMAP3525中文资料应用处理器数据手册TI规格书

描述 Description

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture.
The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:
Streaming video Video conferencing High-resolution still image The device supports high-level operating systems (HLOSs), such as:
Linux® Windows® CE Android™ This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.
The following subsystems are part of the device:
Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8microprocessor IVA2.2 subsystem with a C64x+ digital signal processor (DSP)core PowerVR SGX subsystem for 3D graphics acceleration to support display(OMAP3530 deviceonly) Camera image signal processor (ISP) that supports multiple formats andinterfacing options connected to a wide variety of image sensors Display subsystem with a wide variety of features for multiple concurrent imagemanipulation, and a programmable interface supporting a wide variety of displays. The displaysubsystem also supports NTSC and PAL video out. Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth datatransfers for multiple initiators to the internal and external memory controllers and to on-chipperipherals The device also offers:
A comprehensive power- and clock-management scheme that enables high-performance,low-power operation, and ultralow-power standby features. The device also supports SmartReflexadaptative voltage control. This power-management technique for automatic control of the operatingvoltage of a module reduces the active power consumption. Memory-stacking feature using the package-on-package (POP) implementation (CBBand CBC packages only) OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).
This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections:
Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics Section 4: Clock Specifications input and output clocks, DPLL and DLL Section 5: Video Dac Specifications Section 6: Timing Requirements and Switching Characteristics Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

特性 Features

• OMAP3530 and OMAP3525 Devices:
• MPU Subsystem
• NEON™ SIMD Coprocessor
• High-Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
• Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
• PowerVR® SGX™ Graphics Accelerator (OMAP3530 Device Only)
• Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
• Fine-Grained Task Switching, Load Balancing, and Power Management
• Fully Software-Compatible with C64x and ARM9™
• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
• Six ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
• Load-Store Architecture with Nonaligned Support
• Instruction Packing Reduces Code Size
• Additional C64x+ Enhancements
• Exceptions Support for Error Detection and Program Redirection
• C64x+ L1 and L2 Memory Architecture
• 80KB of L1D Data RAM and Cache (2-Way Set-Associative)
• 32KB of L2 Shared SRAM and 16KB of L2 ROM
• C64x+ Instruction Set Features
• 8-Bit Overflow Protection
• Normalization, Saturation, Bit-Counting
• Additional Instructions to Support Complex Multiplies
• ARM Cortex-A8 Core
• TrustZone®
• MMU Enhancements
• In-Order, Dual-Issue, Superscalar Microprocessor Core
• Over 2x Performance of ARMv6 SIMD
• Jazelle® RCT Execution Environment Architecture
• Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
• ARM Cortex-A8 Memory Architecture:
• 16-KB Data Cache (4-Way Set-Associative)
• 112KB of ROM
• Endianess:
• ARM Data – Configurable
• External Memory Interfaces:
• 16- and 32-Bit Memory Controller with 1GB of Total Address Space
• SDRAM Memory Scheduler (SMS) and Rotation Engine
• General Purpose Memory Controller (GPMC)
• Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
• Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
• System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
• CCD and CMOS Imager Interface
• BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
• Resize Engine
• Separate Horizontal and Vertical Control
• Display Subsystem
• Up to 24-Bit RGB
• Supports Up to 2 LCD Panels
• 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
• Luma and Chroma Separate Video (S-Video)
• Rotation 90-, 180-, and 270-Degrees
• Color Space Converter
• Serial Communication
• 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
• SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
• 128-Channel Transmit and Receive Mode
• Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
• High-, Full-, and Low-Speed Multiport USB Host Subsystem
• Supports Transceiverless Link Logic (TLL)
• One HDQ™/1-Wire® Interface
• Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
• Removable Media Interfaces:
• Comprehensive Power, Reset, and Clock Management
• Dynamic Voltage and Frequency Scaling (DVFS)
• Test Interfaces
• ETM Interface
• 12 32-Bit General-Purpose Timers
• 1 32-Bit 32-kHz Sync Timer
• 65-nm CMOS Technologies
• Discrete Memory Interface (Not Available in CBC Package)
• 515-pin s-PBGA Package (CBB Suffix), .5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)
• 423-pin s-PBGA Package (CUS Suffix), .65-mm Ball Pitch
• 1.8-V I/O and 3.0-V (MMC1 Only), 0.985-V to 1.35-V Adaptive Processor Core Voltage 0.985-V to 1.35-V Adaptive Core Logic Voltage Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.