OMAP3515中文资料Sitara 处理器：Arm Cortex-A8、3D 图形、LPDDR数据手册TI规格书

描述 Description

devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:Streaming video Video conferencing High-resolution still imageThe device supports high-level operating systems (HLOSs), such as:Linux®Windows® CE Android™This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device:Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only) Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensorsDisplay subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out. Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripheralsThe device also offers:A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption. Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections: Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics Section 4: Clock Specifications input and output clocks, DPLL and DLLSection 5: Video Dac Specifications Section 6: Timing Requirements and Switching Characteristics Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:Streaming video Video conferencing High-resolution still imageThe device supports high-level operating systems (HLOSs), such as:Linux®Windows® CE Android™This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device:Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only) Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensorsDisplay subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out. Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripheralsThe device also offers:A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption. Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections: Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics Section 4: Clock Specifications input and output clocks, DPLL and DLLSection 5: Video Dac Specifications Section 6: Timing Requirements and Switching Characteristics Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

特性 Features

• OMAP3 Devices:
• MPU Subsystem
• NEON™ SIMD Coprocessor
• PowerVR® SGX™ Graphics Accelerator
• Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
• Fine-Grained Task Switching, Load Balancing, and Power Management
• Fully Software-Compatible with ARM9™
• ARM Cortex-A8 Core
• TrustZone®
• MMU Enhancements
• In-Order, Dual-Issue, Superscalar Microprocessor Core
• Over 2x Performance of ARMv6 SIMD
• Jazelle® RCT Execution Environment Architecture
• Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
• ARM Cortex-A8 Memory Architecture:
• -KB Data Cache (4-Way Set-Associative)
• 112KB of ROM
• Endianess:
• ARM Data – Configurable
• External Memory Interfaces:
• 16-Bit-Wide Multiplexed Address and Data Bus
• Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
• Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
• System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
• CCD and CMOS Imager Interface
• BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
• Resize Engine
• Separate Horizontal and Vertical Control
• Display Subsystem
• Up to 24-Bit RGB
• Supports Up to 2 LCD Panels
• 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
• Luma and Chroma Separate Video (S-Video)
• Rotation 90-, 180-, and 270-Degrees
• Color Space Converter
• Serial Communication
• 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
• SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
• 128-Channel Transmit and Receive Mode
• Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
• High-, Full-, and Low-Speed Multiport USB Host Subsystem
• One HDQ™/1-Wire® Interface
• Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
• Removable Media Interfaces:
• Comprehensive Power, Reset, and Clock Management
• Dynamic Voltage and Frequency Scaling (DVFS)
• Test Interfaces
• ETM Interface
• 12 32-Bit General-Purpose Timers
• 1 32-Bit 32-kHz Sync Timer
• 5-nm CMOS Technologies
• Discrete Memory Interface
• 1.8-V I/O and 3.0-V (MMC1 Only), Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.