NB7V585M数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The NB7V585M is a differential 1-to-6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INxb inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML, or LVDS logic levels. The NB7V585M produces six identical output copies of clock or dataoperating up to 7GHz or 10.7Gb/s, respectively. As such, NB7V585M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The 16mA differential CML output structure provides matching internal 50-ohm source terminations, 400mV outputswings when externally terminated with a 50-ohm resistor to VCC and is optimized for low skew and minimal jitter. The NB7V585M is powered with either 1.8V or 2.5V supply and is offered in a low profile 5x5mm 32-pin QFN package.

特性 Features

• Maximum Input Data Rate > 10 Gb/s Typical
• Data Dependent Jitter
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter
• Low Skew 1:6 CML Outputs, 30 ps Max
• 2:1 MultiLevel Mux Inputs
• 175 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Operating Range: VCC = 1.71 V to 1.89 V
• Internal 50-ohm Input Termination Resistors
• VREFAC Reference Output
• 40C to +85C Ambient Operating Temperature

应用 Application

• Clock Distribution: SONET/SDH, Fibre Channel, Gigabit Ethernet
• Routers, Servers

简介

NB7V585M属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB7V585M时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。