T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

文件：424.09 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

文件：650.4 Kbytes 页数：38 Pages

ZARLINK

Zarlink Semiconductor Inc

T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

文件：424.09 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

文件：101.08 Kbytes 页数：14 Pages

Mitel

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

文件：101.08 Kbytes 页数：14 Pages

Mitel

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

文件：72.85 Kbytes 页数：19 Pages

Mitel

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

文件：72.85 Kbytes 页数：19 Pages

Mitel

Global Digital Trunk Synchronizer

Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

文件：122.3 Kbytes 页数：16 Pages

Mitel