Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

文件：491.07 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

文件：491.07 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

文件：491.07 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

文件：491.07 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

Advanced T1/CEPT Digital Trunk PLL

Description\nThe MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmis • Provides T1 clock at 1.544 MHz locked to an 8kHz reference clock (frame pulse)\n• Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock\n• Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak\n•Typical jitter atten;

Microchip

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