128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

文件：187.15 Kbytes 页数：17 Pages

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

文件：187.15 Kbytes 页数：17 Pages

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

文件：187.15 Kbytes 页数：17 Pages

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

文件：187.15 Kbytes 页数：17 Pages

AUSTIN