MT28S4M16LC中文资料镁光数据手册PDF规格书

GENERAL DESCRIPTION

This SyncFlash® data sheet is divided into two major sections. The SDRAM Interface Functional Description details compatibility with the SDRAM memory, and the Flash Memory Functional Description specifies the symmetrical-sectored flash architecture functional commands.

FEATURES

• 100 MHz SDRAM-compatible read timing

• Fully synchronous; all signals registered on

positive edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access

• Programmable burst lengths: 1, 2, 4, 8, or full page

(READ)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

– Additional VHH hardware protect mode (RP#)

• Four-bank architecture supports true concurrent

operations with zero latency:

Read from any bank while performing a

PROGRAM or ERASE operation to any other

bank

• Deep power-down mode: 300µA maximum

• Cross-compatible Flash memory command set

• Industry-standard, SDRAM-compatible pinouts

– Pins 36 and 40 are no connects for SDRAM