MSC8144数据手册恩XP中文资料规格书

描述 Description

Overview The MSC8144 processor is the third generation of Our high-performance multicore DSP devices that target wireline and wireless infrastructure applications. It builds on the success of previous multicore DSPs and is designed to bolster the rapidly expanding voice/video/data triple-play services in this space. This multicore DSP delivers the industry's highest level of performance and integration, combining four fully-programmable StarCore® DSP cores, each running at up to 1 GHz with an architecture highly optimized for voice, fax, video and data compression processing.
An internal QUICC Engine® dual-RISC packet-processor supports multiple networking protocols to guarantee reliable data transport over packet networks while significantly offloading such processing from the DSP cores.
The MSC8144 embeds the industry's largest internal memory and supports a variety of advanced interface types, including high-speed Ethernet and UTOPIA for network communications, DDR controller for high-speed, industry-standard memory interface, multi-channel TDM interfaces for connectivity to the PSTN networks, and Serial RapidIO® and PCI interfaces for connectivity to other devices mounted on the same rack or circuit board. 
As a highly flexible, fully programmable, and powerful multimedia DSP, the MSC8144 offers tremendous processing power while maintaining a competitive price and power per channel.
Archived content is no longer updated and is made available for historical reference only.

特性 Features

•Four 800 MHz/1 GHz StarCore® SC3400 DSP extended cores
•16 ALUs deliver up to 12800/16000 MMACS

•Performance equivalent to a 3.2/4.0 GHz SC3400 core




•Each extended core includes the DSP core processor and dedicated instruction cache, data cache, memory management unit (MMU), interrupt controller (EPIC), and timers

•Industry's largest on-chip memory
•Four 16 KB L1 instruction cache (one per core) 

•Four 32 KB L1 data cache (one per core)

•One 128 KB shared L2 instruction cache

•One 512 KB shared M2 memory for critical data and temporary data buffering

•10 MB of 128-bit wide shared M3 memory that eliminates the need for external memory for most applications

•96 KB of boot ROM accessible from all four cores supports boot via serial RapidIO, PCI, I²C and Ethernet interfaces. 




•DDR memory controller with a clock rate up to 200 MHz (400 MHz data rate), 16/32-bit DDR SDRAM data bus with 64 MB to 4 GB DDR and DDR2 devices with x8/x16 data ports (no direct x4 support), configurations up to 1 GB, including up to two physical banks (chip selects), each independently addressable, with double-bit error detection and single-bit error correction (ECC)

•Internal DMA controller with 16 bidirectional time-multiplexed channels enabling data transfers between the internal memories and the serial interfaces

•Eight independent time division multiplex (TDM) interfaces with 2048 DS-0 (64 kbps) channels divided among the eight TDM interfaces

•QUICC Engine communications processor that configures and controls the two Ethernet and the ATM (UTOPIA) interface and offloads handling of the communication tasks from the DSP cores. It includes two 32-bit RISC processors, 48 Kbytes of multi-master multi-port RAM, 48 Kbytes of instruction RAM, a serial DMA channel, control hardware, baud-rate generators, clock synthesizer, interrupt controller and three communication controllers.

•Two GB Ethernet controllers supporting 10/100/1000 Mbps operation using MII, RMII, SMII, RGMII, and SGMII physical interfaces

•One ATM controller supporting a UTOPIA interface and AAL0, AAL2 and AAL5 operation

•Serial RapidIO port supporting 1x/4x operation and a messaging unit

•PCI interface designed to comply with PCI specification revision 2.2 operating at 33 or 66 MHz and 3.3-volt

•UART for an RS-232 interface

•Serial peripheral interface (SPI)

•I²C interface to boot from EEPROM

•Interrupt system that includes an enhanced programmable interrupt controller (EPIC) for each core with up to 256 interrupts and 32 priority levels,  up to 32 virtual interrupts and a virtual NMI generated by a simple write access, and an interrupt concentrator that uses external interrupt outputs

•Sixteen 16-bit programmable timers in four quad-timer modules, two 32-bit general-purpose timers per core, and four software watchdog timer modules

•32 GPIOs, 16 of which can be configured as external maskable interrupts (IRQs)

•Eight programmable hardware semaphores

•Debugging capability through the JTAG interface and OCE30 module, debug and profiling capability in most device modules


The MSC8144 device is manufactured in CMOS 90 nm SOI process technology. The device uses a 29 mm x 29 mm flip chip ball-grid array (FC-BGA) package, available with lead-free spheres.