MPC2104P中文资料摩托罗拉数据手册PDF规格书

The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

All of these cache modules are plug and pin compatible with each other.

• PowerPC–Style Burst Counter On Chip

• Pipeline Data I/O

• Plug and Pin Compatibility

• Multiple Clock Pins for Reduced Loading

• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible

• Three State Outputs

• Buffered Addresses to Data RAMs for Reduced Loading

• Fast Module Clock Rates: Up to 66 MHz

• Fast SRAM Access Times: 9 ns for Tag RAM Match 8 ns for Data RAM

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• 178 Pin Card Edge Module

• Burndy Connector, Part Number: ELF178KSC–3Z50